1. Field of the Invention
This invention is related to the field of processors and, more particularly, to the handling of interrupts.
2. Description of the Related Art
The x86 architecture (also known as the IA-32 architecture) has enjoyed widespread acceptance and success in the marketplace. Accordingly, it is advantageous to design processors according to the x86 architecture. Such processors may benefit from the large body of software written to the x86 architecture (since such processors may execute the software and thus computer systems employing the processors may enjoy increased acceptance in the market due to the large amount of available software).
As computer systems have continued to evolve, 64 bit address size (and sometimes operand size) has become desirable. A larger address size allows for programs having a larger memory footprint (the amount of memory occupied by the instructions in the program and the data operated upon by the program) to operate within the memory space. A larger operand size allows for operating upon larger operands, or for more precision in operands. More powerful applications and/or operating systems may be possible using 64 bit address and/or operand sizes.
Unfortunately, the x86 architecture is limited to a maximum 32 bit operand size and 32 bit address size. The operand size refers to the number of bits operated upon by the processor (e.g. the number of bits in a source or destination operand). The address size refers to the number of bits in an address generated by the processor. Thus, processors employing the x86 architecture may not serve the needs of applications which may benefit from 64 bit address or operand sizes.
In addition, there are various operating system (OS) support features of the x86 architecture which are not widely used in practice, but which may complicate the design and verification of a given implementation or the addition of useful architectural extensions. One example of this is the built-in task switching support, whereby a single control transfer instruction may automatically cause the entire register state of the running program (commonly called the context) to be stored to a system data structure known as the Task State Segment (TSS), and the context of a different program to be loaded from a second TSS, including the Instruction Pointer at which to start execution. This task switching operation may also be initiated by an exception, software interrupt, or external hardware interrupt.
Although the intent of this task switching feature was to automate a large part of the common OS procedure of switching between programs, it eliminates flexibility that OS writers typically prefer, and which they can gain by writing their own context-switching sequences using basic instructions. Hence, most all mainstream x86 operating systems typically use their own sequences to handle context switching, along with their own software data structures rather than the TSS.
There is however one aspect of the TSS which is still used in many systems to support exceptions and interrupts, and which is required by architectural definition. When an exception or interrupt occurs, the processor responds with a control transfer to a special code sequence intended to deal with such an event. The special code sequence typically runs in supervisor mode. The address of this special code sequence, or routine, is retrieved by the processor from an Interrupt Descriptor Table (IDT), using an index (the exception vector) into the IDT that is specific to the type of exception that occurred (e.g. one exception vector may correspond to a page fault while another corresponds to an overflow exception). Before loading the address of the routine into the Instruction Pointer (EIP) register to complete the control transfer, the original EIP value is saved for later inspection or resumption of the interrupted sequence by pushing it onto the stack. For a user-mode exception/interrupt the original stack pointer (ESP) must also be saved and loaded with a new value pointing to the exception handler""s stack, since the x86 architecture requires separate stacks for different privilege levels. This new stack is where the original EIP and ESP values are saved. The pointer to this new stack is retrieved from a location in the TSS structure, and the original instruction pointer (EIP) and stack pointer (ESP) are saved on that new stack. Hence even if the built-in task switching is not used, a TSS must be set up simply to hold this stack pointer. Typically, since there is only one instance of the supervisor program, there need be only one instance of the supervisor stack, and hence only one such TSS is needed.
Although this mechanism suffices for handling routine application exceptions such as page faults or numerical errors, there are at least two cases where this is not sufficient. When a processor is running in supervisor mode it can be susceptible to the same exceptions and interrupts as a user-mode application. In this case, since it is already in supervisor mode and no change in privilege level is required, the stack pointer does not need to be switched and the exception information is just written to the stack indicated by the current stack pointer. But for certain types of faults this can lead to a situation where no forward progress can be made. For example, if the current stack pointer became corrupted and pointed to a virtual page which was not mapped to physical memory, a reference to the top of the stack would cause a page fault exception. In response to this page fault exception, the processor would try to write the exception information to the stack indicated by the stack pointer, incurring another page fault exception known architecturally as a Double Fault. A Double Fault is itself a distinct exception condition with an associated interrupt vector. If, in response to the Double Fault, the processor again attempts to write to the stack, it will again incur the Page Fault exception. This situation is known as a Triple Fault, and a this point the processor halts and enters Shutdown state.
In order to properly handle this situation, a Task Gate descriptor must be used in the IDT for the Double Fault exception vector, instead of a Trap or Interrupt Gate. This causes the processor to do a complete task switch using the built-in task switching feature, regardless of privilege level, which establishes a known good stack. In this situation, most of the exception state is available in the TSS, but any error code associated with the exception will be pushed on the new stack.
However, because the above task switching support mechanism of the x86 architecture is not widely used in mainstream operating systems and its full implementation may complicate the design and verification of useful architectural extensions, and because certain features of the TSS are required by the architecture, a new mechanism is desired which ensures a known good stack.
The problems outlined above are in large part solved by a method and mechanism as described herein.
Broadly speaking, a processor configured to perform an unconditional stack switch and ensure a good stack pointer is contemplated. The processor includes a processing unit coupled to a memory. The memory comprises a plurality of stacks, a data structure, and a descriptor table. The processor is configured to detect interrupts and access a descriptor corresponding to the interrupt within the descriptor table. The descriptor table includes a number of descriptors, each of which includes an index corresponding to entries in an interrupt stack table within the data structure. Subsequent to accessing the descriptor, the processor is configured to access the index within the descriptor in order to determine whether or not an interrupt stack table mechanism is enabled. In response to detecting the interrupt stack table is enabled, the index is used to select an entry in the interrupt stack table. The selected entry in the interrupt stack table indicates a stack pointer which is then used to perform a stack switch.
In one embodiment, the processor is configured to operate in either a legacy mode or a long mode. When operating in a legacy mode, the processor is configured to utilize an existing stack switch mechanism. However, when operating in a long mode, the processor is configured to have access to the interrupt stack switch mechanism.